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LTC4556 Smart Card Interface with Serial Control
FEATURES
s s
DESCRIPTIO
s s
s s s s s s s s
Electrical Specifications Are ISO7816-3 and EMV Compatible Control/Status Serial Port May be Daisy-Chained for Multicard Applications Automatic Shutdown on Electrical Faults Buck Boost Charge Pump Generates 5V, 3V or 1.8V Outputs (Smart Card Classes A, B and C) Automatic Level Translation Dynamic Pull-Ups Deliver Fast Signal Rise Times* Supervisory Functions Prevent Smart Card Faults Low Operating Current: 250A Typical VIN: 2.7V to 5.5V Ultralow Shutdown Current >10kV ESD on Smart Card Pins Small 24-Pin 4mm x 4mm QFN Package
The LTC(R)4556 provides all necessary power control, level translation and supervisory functions for a smart card or S.A.M. card interface. The part contains a low noise charge pump** plus LDO for generating VCC power, as well as all necessary level shifting circuitry. The card voltage can be set to either 1.8V, 3V or 5V. The LTC4556 includes a card detection channel with automatic debounce circuitry. To reduce wiring costs, the LTC4556 interfaces to a microcontroller via a simple 4-wire serial interface. Multiple devices may be connected in daisychain fashion so that the number of wires to the card socket board is independent of the number of sockets. Status data is returned over the same interface. Extensive security features ensure proper deactivation sequencing in the event of a supply fault or a smart card electrical fault. The smart card pins can withstand greater than 10kV ESD in-situ with no additional components. The LTC4556 is available in a small, low profile (0.75mm), 4mm x 4mm QFN package.
, LTC and LT are registered trademarks of Linear Technology Corporation. *U.S. Patent No. 6,356,140 **U.S. Patent No. 6,411,531
APPLICATIO S
s s s s s s
Handheld Payment Terminals Pay Telephones ATM Machines POS Terminals Computer Keyboards Multiple S.A.M. Sockets
TYPICAL APPLICATIO
240k 1 10 INPUT POWER 0.1F 1F 8 6 21 4-WIRE COMMAND INTERFACE 22 23 24 DVCC VBATT
180k 20 UNDERV PRES LTC4556 19
GND FAULT DIN DOUT SCLK LD
C8 C4 I/O RST CLK VCC
18 17 16 15 14 13 1F
4556 TA01
SMART CARD
2 4-WIRE CARD INTERFACE 3 4 5
DATA RIN SYNC ASYNC C+ C- 11 9 CPO 12 1F 1F
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Deactivation Sequence
RST 5V/DIV CLK 5V/DIV I/O 5V/DIV VCC 5V/DIV 10s/DIV
4556 G11.eps
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U
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LTC4556
ABSOLUTE
AXI U RATI GS
VBATT, DVCC, CPO, FAULT, UNDERV to GND ....................................... -0.3V to 6.0V PRES, DATA, RIN, SYNC, ASYNC, LD, DIN, SCLK to GND ............... -0.3V to (DVCC + 0.3V) I/O, CLK ....................................... -0.3V to (VCC + 0.3V)
PACKAGE/ORDER I FOR ATIO
TOP VIEW
UNDERV PRES SCLK DOUT DIN
LD
24 23 22 21 20 19 DVCC 1 DATA 2 RIN 3 SYNC 4 ASYNC 5 FAULT 6 7
NC
25
8
GND
9 10 11 12
C- VBATT C+ CPO
UF PACKAGE 24-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 125C, JA = 37C/W EXPOSED PAD (PIN 25) IS SGND. MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER Input Power Supply VBATT Operating Voltage IVBATT Operating Current IVBATT Shutdown Current DVCC Operating Voltage IDVCC Operating Current IDVCC Shutdown Current Charge Pump ROLCP 5V Mode Open-Loop Output Resistance CPO Turn On Time VBATT = 3.075V, ICPO = ICC = 60mA, (Note 3) ICC = 0mA, 10% to 90%
q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
VCC = 5V, ICC = 0A No Card Present, VCPO = 0V
2
U
U
W
WW U
W
(Note 1)
ICC (Note 5) .......................................................... 65mA VCC Short-Circuit Duration ............................... Indefinite Operating Temperature Range (Note 4) .. - 40C to 85C Storage Temperature Range ................. - 65C to 125C
ORDER PART NUMBER LTC4556EUF
18 C8 17 C4 16 I/O 15 RST 14 CLK 13 VCC
UF PART MARKING 4556
MIN 2.7
TYP
MAX 5.5
UNITS V A A V A A ms
q q q q q
250 0.5 1.7 5 0.2 8.2 0.6
400 1.75 5.5 25 1.5 17 1.5
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LTC4556
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
SYMBOL Smart Card Supply VCC Output Voltage 5V Mode, 0 < ICC < 60mA 3V Mode, 0 < ICC < 50mA 1.8V Mode, 0 < ICC < 30mA ICC = 0mA, 10% to 90% Relative to Nominal Output
q q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 4.65 2.75 1.65 -9 60 15
TYP 5.0 3.0 1.8 0.8 -5 110 32 1 100
MAX 5.35 3.25 1.95 1.5 - 2.5 150 60 2.5 250 0.2
UNITS V V V ms % mA ms A s V V ns MHz
VCC Turn On-Time Undervoltage Detection Overcurrent Detection Smart Card Detection Debounce Time ( Deactivation Time ( PRES to D7)
q
PRES Pull-Up Current RST to VCC = 0.4V) CLK (Non-Bidirectional Modes) Low Level Output Voltage (VOL), (Note 2) High Level Output Voltage (VOH), (Note 2) Rise/Fall Time, (Note 2) CLK Frequency, (Note 2) RST, C4, C8 Low Level Output Voltage (VOL), (Note 2) High Level Output Voltage (VOH), (Note 2) Rise/Fall Time, (Note 2) Low Level Output Voltage (VOL), (Note 2) High Level Output Voltage (VOH), (Note 2) Rise/Fall Time, (Note 2) Short Circuit Current, (Note 2) Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Rise/Fall Time Low Input Threshold (VIL) High Input Threshold (VIH) Input Current (IIH/IIL) DOUT Low Level Output Voltage (VOL) High Level Output Voltage (VOH) UNDERV Threshold Leakage Current
VPRES = 0 ICC = 0mA, CVCC = 1F Sink Current = - 200A Source Current = 200A Loaded with 50pF, 10% to 90%
q q
q q q q
VCC - 0.2 16 10 0.2 VCC - 0.2 100 0.3 0.85 * VCC 500 5 10 0.3 0.8 * DVCC 500 0.15 * DVCC 0.85 * DVCC -1 1 0.3 DVCC - 0.3 1.17 1.23 1.29 50
Sink Current = - 200A Source Current = 200A Loaded with 50pF, 10% to 90% Sink Current = -1mA (VDATA = 0V or VSYNC = 0V) Source Current = 20A (VDATA = VDVCC or VSYNC = VDVCC) Loaded with 50pF, 10% to 90% VDATA = 0V or VSYNC = 0V Sink Current = - 500A (VI/O = 0V or VCLK = 0V) Source Current = 20A (VI/O = VCC or VCLK = VCC) Loaded with 50pF
q q q
V V ns V V ns mA V V ns V V A V V V nA
I/O, CLK (CLK Specifications in Bidirectional Mode Only)
q q q q
DATA, SYNC (SYNC Specifications in Bidirectional Mode Only)
q q q
RIN, DIN, SCLK, LD, SYNC, ASYNC (SYNC Specifications for Non-Bidirectional Mode)
q q q
Sink Current = - 200A Source Current = 200A
q q
q
VUNDERV = 3.3V
q
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LTC4556
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER FAULT Low Level Output Voltage (VOL) Leakage Current Serial Port Timing tDS tDH tDD tL tH tLW tCL tLC DIN Valid to SCLK Setup DIN Valid to SCLK Hold DOUT Output Delay SCLK Low Time SCLK High Time LD Pulse Width SCLK to LD LD to SCLK CLOAD = 15pF 8 8 15 50 50 50 50 0 60 ns ns ns ns ns ns ns ns Sink Current = - 200A VFAULT = 5.5V
q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN
TYP 0.005
MAX 0.3 1
UNITS V A
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This specification applies to all three smart card voltage classes: 1.8V, 3V and 5V. Note 3: ROLCP (2VBATT - VCPO)/ICPO; VCPO will depend upon total load (ICC) and minimum supply voltage VBATT. See Figure 6.
Note 4: The LTC4556E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 5: Based on long term current density limitation.
TYPICAL PERFOR A CE CHARACTERISTICS
No Load Supply Current vs VBATT
500 SHORT-CIRCUIT CURRENT (mA) TA = 25C ICC = 0A 6.0 DVCC = VBATT = 3.3V VCC = 5V OUTPUT RESISTANCE () 9
400 SUPPLY CURRENT (A)
300
VCC = 5V VCC = 3V
200 VCC = 1.8V 100
0 2.7
3.1
3.9 4.3 4.7 5.1 VBATT SUPPLY VOLTAGE (V)
3.5
4
UW
5.5
4556 G01
I/O and CLK Short-Circuit Current vs Temperature (CLK in Bidirectional Mode)
10
Charge Pump Open-Loop Output Resistance vs Temperature (2VBATT - VCPO) / ICPO
VBATT = 2.7V VCPO = 4.9V
5.5
5.0
CLK I/O
8
4.5
7
4.0
3.5 -40
-15
10 35 TEMPERATURE (C)
60
85
4556 G02
6 -40
-15
10 35 TEMPERATURE (C)
60
85
4556 G03
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LTC4556 TYPICAL PERFOR A CE CHARACTERISTICS
VCC Overcurrent Shutdown Threshold vs Temperature
140 VBATT = 3.3V 130 LOAD CURRENT (mA) 120 VCC = 5V, CPO = 5.5V 110 100 90 80 -40 VCC = 3V, CPO = 5.5V VCC = 1.8V, CPO = 4V DEBOUNCE TIME (ms) 45 TA = 85C
I/O LOW OUTPUT VOLTAGE (mV)
-15
10 35 TEMPERATURE (C)
Extra Input Current vs Load Current (IBATT - 2ICC)
6 5 4 3 2 1 0 0.01 VBATT = 3.3V TA = 25C
EXTRA INPUT CURRENT (mA)
SUPPLY CURRENT (A)
2.0 TA = 25C 1.5 1.0
TA = -40C
SUPPLY CURRENT (A)
0.1 1 10 LOAD CURRENT (mA)
Charge Pump and LDO Activation
RST 5V/DIV
VCPO 5V/DIV VCC 5V/DIV I/O 5V/DIV 1ms/DIV
4556 G10
UW
60 85
4556 G04
Card Detection Debounce Time vs VBATT Supply Voltage
50 200
Bidirectional Channel (I/O) Low Output Level vs Temperature
VDATA = VSYNC = 0V IOL = -1mA VBATT = 3V 175 VCC = 1.8V
40
TA = 25C TA = -40C
150
VCC = 3V, 5V
35
125
30
25 2.7
3.1
3.9 4.3 4.7 5.1 VBATT SUPPLY VOLTAGE (V)
3.5
5.5
100 -40
-15
10 35 TEMPERATURE (C)
60
85
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VBATT Shutdown Current vs Supply Voltage
3.0 VDVCC = VBATT 2.5
DVCC Shutdown Current vs Supply Voltage
1.0 VBATT = VDVCC 0.8
0.6
TA = 25C
0.4
TA = -40C TA = 85C
TA = 85C 0.5 0 2.7
0.2
100
4556 G07
3.1
3.9 4.3 4.7 5.1 VBATT SUPPLY VOLTAGE (V)
3.5
5.5
0 2.7
3.1
3.5 3.9 4.3 4.7 5.1 VDVCC SUPPLY VOLTAGE (V)
5.5
4556 G08
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Deactivation Sequence
Data - I/O Channel
CLK 5V/DIV I/O 5V/DIV VCC 5V/DIV
I/O 2V/DIV
DATA 2V/DIV
10s/DIV
4556 G11.eps
100ns/DIV
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LTC4556
PI FU CTIO S
DVCC (Pin 1): Power. Reference voltage for the control logic. DATA (Pin 2): Input/Output. Microcontroller side data I/O pin. The DATA pin provides the bidirectional communication path to the smart card. The card may be selected to communicate via the DATA pin. If several LTC4556s are connected in parallel, the DATA pin can be made high impedance by selecting neither card socket. The C4 and C8 synchronous card pins can be selected to connect to the DATA pin via the serial port (see Table 4). RIN (Pin 3): Input. The RIN pin supplies the RST signal to the smart card. It is level shifted and transmitted directly to the RST pin of a selected card. When the card is deselected, the RST pin is latched at its current state. SYNC (Pin 4): Input-Input/Output. The SYNC pin provides the clock input for synchronous smart cards. When a synchronous card is selected, its CLK pin follows SYNC directly. When a synchronous card is deselected, the CLK pin is latched at its current state. In bidirectional mode, the SYNC pin becomes an input/output with the smart card CLK pin. ASYNC (Pin 5): Input. The ASYNC pin provides the clock input for asynchronous cards and should be connected to a free running clock. The clock signal to the smart card can be a /1, /2, /4 or /8 version of the signal on ASYNC. Asynchronous cards can also be placed in clock stop mode with the clock stopped either high or low. FAULT (Pin 6): Output. The FAULT pin can be used as an interrupt to a microcontroller to indicate when a fault has occurred. It is an open drain output, which is logically equivalent to D4 . (See Table 1) NC (Pin 7): No Connection to chip. May be grounded. GND (Pin 8): Ground. Power ground for the chip. This pin should be connected directly to a low impedance ground plane. C -, C + (Pins 9, 11): Charge Pump. Charge pump flying capacitor pins. A 1F X5R or X7R ceramic capacitor should be connected from C + to C -. VBATT (Pin 10): Power. Supply voltage for analog and power sections of the LTC4556. CPO (Pin 12): Charge Pump. CPO is the output of the charge pump. When the smart card requires power, the charge pump will charge CPO to either 3.7V or 5.35V depending on what smart card voltage is required. A low impedance 1F X5R or X7R ceramic capacitor is required on CPO. VCC (Pin 13): Card Socket. The VCC pin should be connected to the VCC pin of the smart card socket. The activation of the VCC pin is controlled by the serial port (see Tables 1 and 2) and can be set to 0V, 1.8V, 3V or 5V. CLK (Pin 14): Card Socket. The CLK pin should be connected to the CLK pin of the smart card socket. The CLK signal can be derived from either the SYNC input or the ASYNC input depending on which type of card is being accessed. The card type is selected via the serial port (see Tables 1 and 3). In bidirectional mode, the CLK pin becomes an input/output with the microcontroller side SYNC pin. RST (Pin 15): Card Socket. This pin should be connected to the RST pin of the smart card socket. The RST signal is derived from the RIN pin. When the card is selected, its RST pin follows RIN. When the card is deselected, the RST pin holds the current value on RIN. I/O (Pin 16): Card Socket. The I/O pin connects to the I/O pin of the smart card socket. When the smart card is selected, its I/O pin connects to the DATA pin. When the smart card is deselected, its I/O pin returns to the idle state (H). C4, C8 (Pins 17, 18): Card Socket. These pins connect to the C4 and C8 pins of synchronous memory cards on the smart card socket. The signal for these pins is unidirectional and can only be sent to the card. Data for C4 and C8 is transmitted via the DATA pin and may be selected in place of I/O via the serial port (see Table 4). When either C4 or C8 is selected, it will follow the DATA pin. When it is deselected, it will remain latched at its current state. PRES (Pin 19): Card Socket. The PRES pin is used to detect the presence of a smart card. It should be connected to a normally open detection switch on the smart card acceptor's socket. This pin has a pull-up current source on-chip so no external components are required.
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LTC4556
PI FU CTIO S
UNDERV (Pin 20): Input. The UNDERV pin provides security by supplying a precision undervoltage threshold for external supply monitoring. An external resistive voltage divider programs the desired undervoltage threshold. Once UNDERV falls below 1.23V, the LTC4556 automatically begins the deactivation sequence. If external supply monitoring is not required, the UNDERV pin should be connected to either VBATT or DVCC. DIN (Pin 21): Input. Input for the serial port. Command data is shifted into DIN synchronously with SCLK. DIN can be connected directly to a microcontroller or the DOUT pin of another LTC4556 or LTC1955 for daisy chained operation. DOUT (Pin 22): Output. Output for the serial port. Smart card status data is shifted out of DOUT synchronously with SCLK. DOUT can be connected directly to a microcontroller or the DIN pin of another LTC4556 or LTC1955 for daisy chained operation. SCLK (Pin 23): Input. The SCLK pin clocks the serial port. Each new data bit is received on the rising edge of SCLK. SCLK should be left high during idle times and should not be clocked when LD is low. LD (Pin 24): Input. The falling edge of this pin loads the current state of the shift register into the command register. Command changes to the smart card will be updated on the falling edge of LD. The rising edge of LD latches status information into the shift register for the next read/ write cycle. SGND (Pin 25): Exposed Pad. Must be soldered to PCB Ground.
BLOCK DIAGRA
W
U
U
U
CHARGE PUMP C+ 11 C- 9 GND 8 VBATT 10 CPO 12
CHARGE PUMP
LDO
13 VCC 16 I/O
17 C4 DATA 2 ASYNC 5 SMART CARD COMMUNICATIONS SYNC 4 CLOCK CONTROL LOGIC RESET CONTROL LOGIC 18 C8 SMART CARD SOCKET
14 CLK
RIN 3
15 RST
19 PRES
6 STATUS DATA
FAULT
DIN 21 SERIAL PORT COMMAND/STATUS DATA DOUT 22 SCLK 23 LD 24 SHIFT REGISTER 1 DVCC DIGITAL SUPPLY
-
COMMAND LATCH
20 UNDERV
+
1.23V
+ -
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LTC4556
OPERATIO
Serial Port The microcontroller compatible serial port provides all of the command and control inputs for the LTC4556 as well as the status of the smart card. Data on the DIN input is loaded on the rising edge of SCLK. D7 is loaded first and D0 last. At the same time the command bits are being shifted into the DIN input, the status bits are being shifted out of the DOUT output. The status bits are presented to DOUT on the rising edge of SCLK. Once all bits have been clocked into the shift register, the command data is loaded into the command latch by bringing LD low. At this time the command latch is updated and the LTC4556 will begin to act on the new command set. When LD is low, the shift register is transparent to the status data of the smart card channel. The status data is latched into the shift register on the rising edge of LD. SCLK should be held in the high state when idle and should only be clocked when LD is high. Likewise LD should only be brought high when SCLK is high. Figure 2 shows the operation of the serial port. Multiple LTC4556s may be daisy chained together by connecting the DOUT pin of one LTC4556 to the DIN pin of another. Figure 7 shows an example of an LTC4556 daisy chained together with LTC1955s. The maximum clock rate for the serial port is 10MHz. The serial port controls the following parameters of the smart card socket: * Selection/deselection of the smart card * VCC voltage level of the card (5V/3V/1.8V/0V)
tLC SCLK tDS tDH tDD tH tL tCL tLW
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* Clock mode of the card (synchronous, asynchronous or bidirectional) * Operating mode of asynchronous cards (clock stop high, low, /1, /2, /4 or /8) * Selection of the I/O, C4 or C8 pins The serial port provides the following status data: * It indicates the presence or absence of the smart card. * It indicates the readiness of the smart card VCC supply. Communication with the smart card is disabled until its power supply voltage has reached the final value. * It indicates fault status. In the event of an electrical or ATR fault, the fault is reported. For electrical faults, the LTC4556 will automatically deactivate the smart card. Table 1 illustrates the command inputs and status outputs associated with each bit of the serial data word. Three voltage options are available from the LTC4556: 5V, 3V and 1.8V. Bits D0, D1 determine which voltage is selected. Setting both control bits to 0 deactivates the card and sets the smart card supply voltage to 0V. Table 2 shows the operation of the supply control bits. The CLK pin to the smart card can be programmed for various modes. Both synchronous and asynchronous cards are supported. There are several options available with asynchronous cards. Table 3 shows how all clock options are obtained using bits D5-D7.
DIN X D7 D6 D2 D1 D0 X LD D7 FROM INPUT DOUT D7 D6 D5 D1 D0 D7
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Figure 2. Serial Port Timing Diagram
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LTC4556
OPERATIO
STATUS OUTPUT 0 0 0 0 Card Electrical Fault Card ATR Fault Card VCC Ready Card Present
Table 1. Serial Port Commands
BIT D0 D1 D2 D3 D4 D5 D6 D7 COMMAND INPUT VCC Options (See Table 2) Card Select/Deselect Card Communications Options (See Table 4) Card Clock Options (See Table 3)
Table 2. VCC and Shutdown Options
D1 0 0 1 1 D0 0 1 0 1 STATUS VCC = 0V (Shutdown) VCC = 1.8V VCC = 3V VCC = 5V
Table 3. Clock Options
D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 CLOCK MODE Synchronous Mode Bidirectional Mode Asynchronous Stop Low Asynchronous Stop High Asynchronous /1 Asynchronous /2 Asynchronous /4 Asynchronous /8
To receive status data from the serial port, a read/write operation must be performed. When polling for the presence of a smart card, the input word may be set to $00 since this is the shutdown command for the LTC4556. Data Channel The data channel is level shifted to the appropriate VCC voltages at the I/O pin. An NMOS pass transistor performs the level shifting. The gate of the NMOS transistor is biased such that the transistor is completely off when both sides have relinquished the channel. If one side of the channel asserts an L, then the transistor will convey the L to the other side.
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Note that current passes from the receiving side of the channel to the transmitting side. The low output voltage of the receiving side will be dependent upon the voltage at the transmitting side plus the IR drop of the pass transistor. When a card socket is selected, it becomes a candidate to drive data on the DATA pin and likewise receive data from the DATA pin. When a card socket is deselected, the voltage on its I/O pin will return to the idle state (H) and the DATA side of that channel will become high impedance. The LTC4556 includes provision for unidirectional communication with the C4 and C8 pins of the smart card. The C4, C8 and I/O pins are individually multiplexed to the DATA pin using bits D3 and D4 as shown in Table 4.
Table 4. Communications Options
D4 0 0 1 1 D3 0 1 0 1 COMMUNICATION MODE Nothing Selected C4 Connected to DATA Pin C8 Connected to DATA Pin I/O Connected to DATA Pin
Dynamic Pull-Up Current Sources The current sources on the bidirectional pins (DATA, I/O) are dynamically activated to achieve a fast rise time with a relatively small static current. Once a bidirectional pin is relinquished, a small start up current begins to charge the node. An edge rate detector determines if the pin is released by comparing its slew rate with an internal reference value. If a valid transition is detected, a large pull-up current enhances the edge rate on the node. The higher slew rate corroborates the decision to charge the node thereby affecting a dynamic form of hysteresis.
LOCAL SUPPLY
+ -
dv dt
VREF
ISTART
BIDIRECTIONAL PIN
4556 F03
Figure 3. Dynamic Pull-Up Current Sources
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LTC4556
OPERATIO
Clock Channel As described in the section Serial Port, the LTC4556 supports both synchronous and asynchronous smart cards. When bits D5-D7 are set to 0s, the clock channel is in synchronous mode. In synchronous mode, the CLK pin follows the SYNC pin for a channel that is selected. If the channel is deselected (via the serial port) the CLK line is latched at its current value. When control bits D7, D6 and D5 are set to 0, 0 and 1 respectively, the clock channel is in bidirectional mode. This mode permits clock stretching when communicating with bidirectional cards. The bidirectional level translation circuit is identical to the I/O-DATA circuit. A low can be asserted from either the SYNC pin or the CLK pin and the other pin will follow. The low can be "handed off" to affect clock stretching if both sides assert at the same time. It will not run as fast as the unidirectional synchronous or asynchronous modes but does employ accelerating pullup sources on both sides for maximum clock rate. In asynchronous mode the CLK pin follows either the ASYNC pin (/1 mode) or a divided version of this pin. The CLK pin can also be stopped high or low. The available divider ratios include /2, /4 and /8. When switching between divider ratios, the internal selection circuitry ensures that no spikes or glitches appear on the CLK pin. Consequently, it may take up to 8 clock pulses for the clock frequency change command to take affect. Synchronization circuitry ensures that no glitches occur when entering or exiting one of the stop modes. For example, when entering Stop Low mode, the selection circuitry waits for the next falling edge of the CLK signal to make the change. Likewise if Stop High is selected it will occur on the next rising edge. Deselection of an asynchronous card does not affect its CLK pin. Its clock can be started, stopped or its divider ratio changed at any time. To clean up the duty cycle of the incoming clock in asynchronous applications, any of the clock divider modes /2, /4 or /8 will yield a very nearly 50% duty cycle.
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Additional synchronization circuitry prevents glitches from occurring when switching between synchronous mode and asynchronous mode. Because of this circuitry, two edges (a falling edge followed by a rising edge) are necessary at the CLK pin to switch modes from asynchronous to synchronous. For example, if clock stop mode is engaged, the clock channel will not change modes until clock stop mode is disengaged. Both SYNC and ASYNC inputs are independently level shifted to the appropriate voltage for the CLK pin (5V, 3V, 1.8V). Reset Channel When the card is selected, the reset channel provides a level shifted path from the RIN pin to the RST pin. When the card is deselected its RST pin is latched at the current value of RIN. Smart Card Detection Circuit The PRES pin is used to detect the presence of a smart card. An automatic debounce circuit waits until a smart card has been present for a continuous period of typically 32ms. Once a valid card indication exists, the status bit is updated and may be polled by cycling data through the serial port. The DOUT pin (equivalent to D7) of the serial port can be used to indicate the presence of a card in real time if LD is held low. The PRES pin has a built-in pull-up current source so no external components are required for switch detection. The pull-up current source is designed to have a small current when the pin voltage is below approximately 1V but somewhat higher current when the pin voltage reaches 1V. This helps maintain low power dissipation when a card is present and yet fast response time to a card removal. Activation/Deactivation For maximum flexibility, the activation sequencing of the smart card is left to the application programmer. However, deactivation can be achieved either manually or automatically. An electrical fault condition will trigger the automatic deactivation.
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OPERATIO
The built-in deactivation sequence can be executed via the serial port simply by setting the control bits D0 and D1 to 0. The deactivation sequence is outlined below. 1. The RST pin is immediately brought low. 2. The deactivation of the CLK pin depends upon which type of card is used: If the smart card was set to asynchronous mode then the CLK pin will be latched low on its next falling edge. If no falling edges occur within 5s (min) then the CLK line is forced low. If the smart card was set to synchronous mode then the CLK pin is immediately latched at its current value (either high or low) and then forced low after a duration of 5s (min). During the 5s timeout period, changes on SYNC will be ignored. 3. The I/O, C4 and C8 pins are brought low. 4. The VCC pin is brought low. Upon activation, to comply with relevant smart card standards, none of the smart card signal pins will be allowed to go high before the smart card supply voltage (VCC) has reached its final value. Electrical Fault Detection Several types of faults are detected by the LTC4556. They include VCC undervoltage, VCC overcurrent, CLK, RST, C8, C4 short circuit, card removal during a transaction, failed answer to reset (ATR), supply undervoltage or UNDERV and chip overtemperature. To prevent false errors from plaguing the microcontroller, the electrical faults are acted upon only after a 5s (min) timeout period. Card removal during transaction faults initiate the deactivation sequence immediately. VCC undervoltage faults are determined by comparing the actual output voltage with the internal reference voltage. If the output is more than ~5% below its set point for the entire timeout period, the fault is reported and the deactivation sequence is initiated.
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VCC overcurrent faults are detected by comparing the output current of the LDOs with an internal reference level. If the current of the LDO is more than 110mA (typ) for the entire timeout period, the fault is reported and the deactivation sequence is initiated. CLK and RST faults are detected by comparing the outputs of these pins with their expected signals. If the signal on a pin is incorrect for the entire timeout period, the fault is reported and the deactivation sequence is initiated. The clock channel is a special case. Since it can have a free running clock, the error indication is accumulated over a longer period of time without being cleared. Even though the clock may be running, an error will still be detected. An overtemperature fault is detected by sensing the junction temperature of the IC. If the junction temperature exceeds approximately 150C for the entire timeout period, the fault is reported by setting the fault bit (D4) and the deactivation sequence is initiated. A card removal fault is determined as soon as the PRES pin is high. Once this occurs the fault is reported and the deactivation sequence is initiated. If no card is present, and the application software attempts to power up a card socket, an automatic fault will result. Short circuits on the I/O line will not be detected by the fault detection hardware; however, a short circuit from I/O to VCC will be compliant with the maximum current limits set by applicable standards (<15mA). The same is true of the CLK pin when it is set to bidirectional mode. Answer to Reset (ATR) Fault Detection Answer to Reset faults are detected by an internal counter that is started once the RST line goes high. If the DATA pin remains high for 40,000 clock cycles, the ATR fault bit is set in the serial port's status register (see Table 1). An ATR fault can not occur if the clock mode is set to synchronous. ATR faults will only occur for asynchronous smart cards.
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LTC4556
OPERATIO
ATR faults are cleared by bringing the RST pin low via RIN. An ATR fault will not automatically deactivate the smart card. It is the application programmer's responsibility to check the status register for ATR faults and deactivate the smart card in accordance with smart card standards. Generally, the application has 50ms (EMV 2.1.3.1, 2.1.3.2) from the 40,000th clock pulse to deactivate the card. Once the LTC4556 receives the deactivation command, it will shut down the smart card in less than 250s.
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Using the FAULT Pin The FAULT pin can be used as an interrupt to a microcontroller. It is an open-drain output and generally requires a pull-up resistor. The FAULT pin will go low when an electrical fault occurs. The FAULT pin is logically equivalent to D4 (see Table 1).
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LTC4556
APPLICATIO S I FOR ATIO
10kV ESD Protection All smart card pins (CLK, RST, I/O, C4, C8 and VCC) can withstand over 10kV of human body model ESD in-situ. In order to ensure proper ESD protection, careful board layout is required. The GND pin should be tied directly to a ground plane. The multilayer ceramic chip VCC capacitor should be located very close to the VCC pin and tied immediately to the ground plane. Capacitor Selection
Warning: A polarized capacitor such as tantalum or aluminum should never be used for the flying capacitor since its voltage can reverse upon start up of the LTC4556. Low ESR ceramic capacitors should always be used for the flying capacitor.
A total of four capacitors are required to operate the LTC4556. An input bypass capacitor is required at VBATT and DVCC. An output bypass capacitor is required on the smart card VCC pin. A charge pump flying capacitor is required from C + to C - and a charge storage capacitor is required on the charge pump out pin CPO. To prevent excessive noise spikes due to charge pump operation, low ESR (equivalent series resistance) multilayer ceramic chip capacitors are strongly recommended. There are several types of ceramic capacitors available each having considerably different characteristics. For example, X7R/X5R ceramic capacitors have excellent voltage and temperature stability but relatively low packing density. Y5V ceramic capacitors have apparently higher packing density but poor performance over their rated voltage or temperature ranges. Under certain voltage and temperature conditions Y5V and X7R/X5R ceramic capacitors can be compared directly by case size rather than specified value for a desired minimum capacitance. Placement of the capacitors is critical for correct operation of the LTC4556. Because the charge pump generates large current steps, all of the capacitors should be placed as close to the LTC4556 as possible. The low impedance
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nature of multilayer ceramic chip capacitors will minimize voltage spikes but only if the power path is kept very short (i.e., minimum inductance). The VBATT node should be especially well bypassed. The capacitor for this node should be directly adjacent to the QFN package. The CPO and flying capacitors should be very close as well. The LTC4556 can tolerate more distance between the LDO capacitor and the VCC pin. Figure 4 shows an example of a tight printed circuit board layout using single layer copper. For best performance a multilayer board can be used and should employ a solid ground plane on at least one layer. The following capacitors are recommended for use with the LTC4556:
TYPE BATT, CPO, CFLY, VCC CDVCC X5R X5R VALUE 1F 0.1F CASE SIZE 0603 0402 MURATA P/N GRM39 X5R 105K 6.3 GRM36 X5R 104K 10
VCC CPO VBATT GND
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Figure 4. Optimum Single Layer PCB Layout
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LTC4556
APPLICATIO S I FOR ATIO
Interfacing to a Microcontroller The serial port of the LTC4556 can be connected directly to a 68HC11 style microcontroller's serial port. The microcontroller should be configured as the master device and its clock's idle state should be set to high (MSTR = 1, CPOL = 1 and CPHA = 0 for the MC68HC11 family). Figure 5 shows the recommended configuration and direction of data flow. Note that an additional I/O line is necessary for LD to load the data once it has shifted around the loop. Command data is latched into the command register on the falling edge of the LD signal. The LTC4556 will begin to act on new command data as soon as LD goes low. Any general purpose microcontroller I/O line can be configured to control the LD pin. The status of the LTC4556 is returned over the serial port. Status data is latched into the shift register on the rising edge of the LD pin. Whenever the system is waiting for status data from the LTC4556, its LD pin should be held low.
CONTROLLER MOSI MISO SCK I/O
Figure 5. Microcontroller Interface
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Daisy-Chained Operation For applications requiring more than one card socket, the serial port of the LTC4556 is designed to be easily daisychained. The DOUT pin of one LTC4556 can be connected directly to the DIN pin of another LTC4556 or LTC1955. Rather than sending one 8-bit byte before asserting LD, the microcontroller should send one 8-bit byte per device. LD should only be asserted after all devices have been updated. Figure 7 shows an LTC4556 cascaded in daisy chain fashion with two LTC1955s. In this case the microcontroller would write five 8-bit bytes before asserting the LD pin.
LTC4556 DIN DOUT CARD SCLK LD
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LTC4556
APPLICATIO S I FOR ATIO
Asynchronous Card Detection
Since the shift register is transparent when LD is held low, DOUT is the same as D7. Recall from Table 1 that D7 indicates the status of the card detection channel. Thus it is not necessary to perform an entire read/write operation to determine the card detection status. With LD low, DOUT can be used to generate a real time card detection interrupt. Using the UNDERV Pin The UNDERV pin can be used to add protection against a supply undervoltage fault. By using two external programming resistors, the undervoltage detection can be set to an arbitrary level (Figure 8). To ensure that the smart card is properly shut down, there must be sufficient energy available in the input bypass capacitor to run it until the deactivation cycle begins. It can take approximately 30s from the detection of a fault until the deactivation sequence begins. It is desirable to maintain the VBATT supply at 2.7V or greater during this period. Consider the following (worst-case) example: 1) The UNDERV pin is programmed to trip below 3.1V. 2) It is possible to have the card activated at 5V and drawing 60mA.
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Since the output voltage is programmed to 5V, the charge pump will be acting as a voltage doubler. With the card drawing 60mA, the input current will be 2 * (60mA) or about 120mA. Allowing the VBATT supply to droop from 3.1V to 2.7V during the 30us timeout period the input capacitance would need to be at least 120mA/[(3.1V - 2.7V)/30s] or 9F. Zero Shutdown Current Although the LTC4556 is designed to have very low shutdown current it can still draw over a microampere on both DVCC and VBATT when in shutdown. For applications that require virtually zero shutdown current, the DVCC pin can be grounded. This will reduce the VBATT current to well under a single microampere. Internal logic ensures that the LTC4556 is in shutdown when DVCC is grounded. Note, however, that all of the logic signals that are referenced to DVCC (DIN, SCLK, LD, DATA, RIN, SYNC and ASYNC) will have to be at 0V as well to prevent ESD diodes to DVCC from being forward biased. Operation at Higher Supplies If a 5.5V to 6V supply voltage is available, it is possible to achieve some power savings by overriding the charge pump. The higher supply can be connected directly to the CPO pin. As long as the voltage on CPO is higher than that at which it ordinarily regulates (5.35V or 3.7V depending on voltage selections) the charge pump's oscillator will not run. This configuration can give considerable power savings since the charge pump is not being used.
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LTC4556
APPLICATIO S I FOR ATIO
A voltage source is still needed on both DVCC and VBATT in this configuration. Recall that DVCC sets the logic reference level for all the control and smart card communication pins. The voltage on VBATT can be any convenient level that meets the parameters in the Electrical Characteristics table. The 5.5V to 6V supply can be left permanently connected to CPO but there will be approximately 5A of current flow into CPO when the LTC4556 is in shutdown. Charge Pump Strength Under low VBATT conditions, the amount of current available to the smart card is limited by the charge pump. Figure 6 shows how the LTC4556 can be modeled as a Thevenin equivalent circuit to determine the amount of current available given the effective input voltage, 2VBATT and the effective open-loop output resistance, ROLCP. From Figure 6, the available current is given by:
ICC 2VBATT - VCPO ROLCP
ROLCP is dependent on a number of factors including the switching term, 1/(fOSC * CFLY), internal switch resistances and the nonoverlap period of the switching circuit. However, for a given ROLCP, the minimum CPO voltage can be determined from the following expression:
Figure 6. Equivalent Open-Loop Circuit
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VCPO 2VBATT - (ICC )ROLCP
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The LDO has been designed to meet all applicable smart card standards for VCC with VCPO as low as 5.13V. Given this information, trade-offs can be made by the user with regard to total consumption (ICC) and minimum supply voltage. Changing the Smart Card Supply Voltage Although the LTC4556 control system will allow the smart card voltage to be changed from one value to the next without an interim power down, this is not recommended. When changing from a higher voltage to a lower voltage there will generally not be a problem; however, changing from a lower voltage to a higher voltage can result in both an undervoltage condition or an overcurrent condition. The likely result is that the LTC4556 will automatically deactivate. Applicable smart card standards specify that the smart card supply be powered to zero before applying a new voltage. Compliance Testing Inductance due to long leads on type approval equipment can cause ringing and overshooot that leads to testing problems. Small amounts of capacitance and damping resistors can be included in the application without compromising the normal electrical performance of the LTC4556 or smart card system. Generally a 100 resistor and a 20pF capacitor will accomplish this as shown in Figure 9.
ROLCP CPO
+ -
2VBATT
LDO
VCC
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LTC4556
APPLICATIO S I FOR ATIO
INPUT POWER
FAULT 4-WIRE COMMAND INTERFACE
4-WIRE CARD INTERFACE
Figure 7. An LTC4556 and Two LTC1955s Daisy Chained Together
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1F 1F 10 9 C- VBATT 8 GND 1 DVCC 20 UNDERV 6 FAULT 21 DIN 22 DOUT 23 SCLK 24 LD 2 DATA 3 RIN 4 SYNC 5 ASYNC 1F 4.7F 12, 13 11 C- 14 C+ 21 PRES B 2 PRES A VENDOR CARD 11 C+ 19 PRES SMART CARD LTC4556 CPO 12 1F VBATT 9, 10 GND 1 DVCC 23 UNDERV 24 FAULT 27 DIN 28 DOUT 26 SCLK 25 LD 29 DATA 30 RIN 32 SYNC 31 ASYNC 1F 4.7F 12, 13 11 C- 14 C+ 21 PRES B 2 PRES A VENDOR CARD VENDOR CARD LTC1955 CPO 15 4.7F VBATT 9, 10 GND 1 DVCC 23 UNDERV 24 FAULT 27 DIN 28 DOUT 26 SCLK 25 LD 29 DATA 30 RIN 32 SYNC 31 ASYNC VENDOR CARD LTC1955 CPO 15 4.7F
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LTC4556
APPLICATIO S I FOR ATIO
LTC4556
Figure 8. Setting the Undervoltage Trip Point
100 I/O 100 CLK LTC4556 RST 20pF VCC 1F 0.1F C1 C5
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100
Fiugre 9. Additional Components for Improved Compliance Testing
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MAIN SUPPLY R1 UNDERV 20 R2 VTRIP = 1.23V (1 + R1/R2)
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C7 20pF C3 20pF C2 SMART CARD SOCKET
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LTC4556
PACKAGE DESCRIPTIO
4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 0.05
4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6)
NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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UF Package 24-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD 0.23 TYP R = 0.115 (4 SIDES) TYP 23 24 0.38 0.10 1 2 2.45 0.10 (4-SIDES)
(UF24) QFN 1103
0.200 REF 0.00 - 0.05
0.25 0.05 0.50 BSC
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LTC4556
TYPICAL APPLICATIO
0.1F
16
17
4 VCC
RXEN DREN
LTC1348CG DB9 RD 2 TD 3 GND 5 7 8 25 24 40 39
DR1OUT RX1IN
DR1IN RX1OUT
PD1 (TXD) PD0 (RXD)
5 0.1F 6 2 0.1F 3
C1+ C1 - C2 + C2
-
27 C3 + 26 C3 - 0.1F
V+ 1 0.1F
V- 28 0.1F
GND 15
VRL VSS MODA EXTAL 18 20 22 26 10M
RELATED PARTS
PART NUMBER LTC1555L/LTC1555L-1.8 LTC1555/LTC1556 LTC1755/LTC1756 LTC1955 LTC1986 LTC4555 LTC4557 DESCRIPTION 1MHz, SIM Power Supply and Level Translator for 1.8V/3V/5V SIM Cards 650kHz, SIM Power Supply and Level Translator for 3V/5V SIM Cards 850kHz, Smart Card Interface with Serial Control for 3V/5V Smart Card Applications Dual Smart Card Interface with Serial Control for 1.8V/3V/5V Smart Card Applications 900kHz, SIM Power Supply for 3V/5V SIM Cards SIM Power Supply and Level Translator for 1.8V/3V SIM Cards Dual SIM/Smart Card Power Supply and Level Translator for 1.8V/3V Cards COMMENTS VIN: 2.6V to 6.6V, VOUT = 1.8V/3V/5V, IQ = 32A, ISD < 1A, SSOP16 VIN: 2.7V to 10V, VOUT = 3V/5V, IQ = 60A, ISD < 1A, SSOP16, SSOP20 VIN: 2.7V to 7V, VOUT = 3V/5V, IQ = 60A, ISD < 1A, SSOP16, SSOP24 VIN: 3V to 5.5V, VOUT = 1.8V/3V/5V, IQ = 200A, ISD < 1A, QFN32 VIN: 2.6V to 4.4V, VOUT = 3V/5V, IQ = 14A, ISD < 1A, ThinSOT VIN: 3V to 6V, VOUT = 1.8V/3V, IQ = 40A, ISD < 1A, QFN16 VIN: 2.7V to 5.5V, VOUT = 1.8V/3V, IQ = 250A, ISD < 1A, QFN16
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ThinSOT is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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Battery-Powered RS232 to Smart Card Interface
FAULT 0.1F 47k RESET 47k 0.1F 180k 262k 4.7F
+
Li-ION
21
45
19
37 4 36 1 5 3
1k VCC18 VCC3 VCCA RST RST LTC1728ES5-1.8 GND 2 38 42 21 22 DIN 6 FAULT
1 DVCC
20 UNDERV
10 VBATT
MOD B VDD VRH XIRQ
MC68L11E9PB2
LTC4556EUF C8 C4 I/O RST
18 17 16 15
C8 C4 C7 C2 C3 C1 1F 0.1F C5 SMART CARD
IRQ (MOSI) PD3
41 (MISO) PD2 43 (SCK) PD4 44 (SS) PD5
DOUT 23 SCLK 24 LD
14 CLK 13 VCC
PRES
19
(2MHz) E PB0 (IC3) PA0 PC0 PA7 PC1
24 9 1 28 46 29
5 3 2 4
ASYNC RIN DATA SYNC
XTAL 27
C- 9
C+ 11
CPO 12 1F
GND 8
8.000MHz 27pF 27pF
1F
4556 TA02
LT/TP 0604 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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